A 2.89mW 50GOPS 16x16 16-Core MIMO Sphere Decoder in 90nm CMOS

論文發表人:  楊家驤 (加州大學洛杉磯分校電機所博士班)

 

http://www.esscirc2009.org/

 

在這篇論文中，我們以90奈米製程實作了一顆具有16核心適用於多重輸入多重輸出通道的球狀解碼器。這顆球狀解碼器晶片擁有高度彈性，能支援多種格規格：從2x2天線陣列到8x8天線陣列，BPSK到64-QAM的調變方式，並且支援16-128載波。操作在16MHz的工作頻率、16x16天線陣列、64QAM模式時，它能提供高達50GOPS的運算量。操作於321mV電壓時，其功率消耗僅2.89mW，產生高達17.3GOPS/mW的功率效率。而操作在256MHz頻率時，使用16MHz的頻率通道，它的最高資料輸出為1.5Gbps。

 

A 16-core multi-input multi-output (MIMO) decoder for agile communication systems is implemented in a low-VT 90nm CMOS technology. This chip implements the sphere decoding algorithm and is highly flexible to support multiple configurations: antenna arrays from 2×2 to 16×16, modulations from BPSK to 64QAM, and up to 128 data streams. Operating at 16MHz, the chip provides 50GOPS (12-bit add equivalent) in the 16×16, 64QAM mode. It consumes 2.89mW of power with a 321mV supply voltage, resulting in a power efficiency of 17.3GOPS/mW. At 256MHz, the peak data rate exceeds 1.5Gbps over a 16MHz channel.