Exploring Asynchronous Logic Circuits via 10-nm Wide Silicon Nanowire FETs

論文發表人:黃若谷( 加州理工學院電機系博士班)

http://www.mrs.org/s_mrs/doc.asp?CID=27791&DID=332913

在本篇論文中，我們成功地利用僅十奈米寬的單晶矽奈米線，來製備高性能的非同步式邏輯電路 (asynchronous logic circuits) 。由於奈米電子元件具有先天上難以避免的大幅度參數變異量 (large parameter variations)，傳統的同步式數位電路 (synchronous logic circuits) 並不適合應用在奈米電子上。而非同步式數位電路的高容錯特性，讓此類電路可以適應奈米電子元件的高參數變異，十分有潛力應用在下一世代的的奈米電子。我們利用本實驗室特有的超晶格奈米線圖形轉換製程 (superlattice nanowire pattern transfer)，搭配表面處理 (surface treatment)，製作出均勻且低缺陷密度的單晶矽奈米線。將此高品質的單晶矽奈米線應用在電晶體 (transistors) 上，展現了高開關電流比 (on-off current ratio)、高載子遷移率 (carrier mobility)、低汲極誘導能障降低 (drain-induced barrier lowing) 以及元件可再現性 (reproducibility)。我們同時製備了反相器電路 (inverter) 和三級環型震盪器 (three-stage ring oscillator) 來探索電路的靜態和動態特性。我們的反相器電路展現了較任何已發表相關文獻都要高的電壓增益 (voltage gain)，並且具有對稱的輸入輸出特性 (matched input/output range)。而我們的三級環型震盪器則展現近乎軌對軌 (rail-to-rail) 的動態輸出特性。證明了我們的奈米單晶矽元件可以更進一步應用在下一代的奈米非同步式數位電路上。 

The speed of synchronous logic circuits, which are the standard of digital circuits, is determined by the worst-case delay of the slowest signal path. Nanoscale synchronous logic circuits could become inefficient because of the long worst-case delay due to the stochastic device variations. Alternatively, asynchronous logic circuits are more robust for nanoelectronics since they are less sensitive to the worst-case delay. We explore silicon nanowire (SiNW) field-effect transistors (FETs) for asynchronous logic applications, via the fabrication and testing of SiNW-based ring oscillators. Arrays of 10-nm wide SiNWs are fabricated by using the superlattice nanowire pattern transfer technique. We report on doping methods, as well as SiNW surface treatments, for producing SiNW FETs that exhibit high performance in terms of large on/off-state current ratios (~108), high carrier mobilities (~269 cm2/V/s), low subthreshold swing (~84 mV/dec), low drain-induced barrier lowering (~30 mV/V) and device-to-device reproducibility. The SiNW inverter demonstrates a sharp transition, high noise margins and the highest voltage gain (~148) reported for a SiNW based NOT gate. The 3-stage SiNW ring oscillator exhibits spontaneous oscillation centered at 13.4 MHz with near rail-to-rail output swing.  Both static and dynamic characteristics indicate that these SiNW-based FETs circuits are excellent candidates for asynchronous nanoelectronics.