A Flexible VLSI Architecture for Extracting Diversity and Spatial Multiplexing Gains in MIMO Channels

論文發表人:  楊家驤 (加州大學洛杉磯分校電機所博士班)

http://www.ieee-icc.org/2008/conference.html

球狀解碼演算法能在多重輸入輸出通道中達到最大概似效能，但它所需的計算複雜度卻大幅減少。這樣的複雜度化簡使得它相當適合於硬體實現。在這篇論文中，我們提出一個具有彈性架構能支援不同天線陣列與調變方式的球狀解碼器架構，進而充分利用多重輸入輸出通道中的多樣－多工增益。我們採用了多種訊號處理與電路技巧來進行硬體複雜度的降低。相對於直接實現的架構，甚至在不考慮支援多重載波的情況下，這個架構已經達到了20倍的面積減少。我們所提的彈性架構能支援2x2到16x16天線陣列，BPSK到64-QAM的調變方式，並且支援16-128載波。使用16MHz的頻寬，資料傳輸速率可高達1.5Gbps。採用90奈米製程，這個電路所需的晶片面積為0.5mm2。

The sphere decoding algorithm is able to approach maximum likelihood (ML) detection with significantly reduced computational complexity for multi-input multi-output (MIMO) communications. The computational reduction makes it attractive for hardware implementation. This paper presents a unified sphere decoder architecture that deploys diversity-multiplexing tradeoff in MIMO channels by taking advantage of the flexibility in the number of antennas and modulation schemes. Several signal processing and circuit techniques are constructively combined to reduce the hardware complexity: a 20 times area reduction is achieved even without interleaving of sub-carriers compared to the direct-mapped architecture. The proposed flexible architecture supports antenna arrays from 2x2 to 16x16, modulations from BPSK to 64-QAM, over 16 to 128 sub-carriers. The peak estimated data rate exceeds 1.5 Gbps over a 16 MHz bandwidth in just 0.55 mm2 in a standard 90 nm CMOS process.