A Scalable Delay Insensitive Asynchronous NoC with Adaptive Routing

論文發表人：王啟峰/加州大學爾灣分校/電機電腦科學系

http://www.ict2010.org/

 

Network-on-Chip (NoC) 在解決傳統處理器匯流排架構的限制提供了非常有效並且可行的方法。然而，隨著NoC的規模增加，系統頻率同步問題成了NoC發展的主要障礙。大型同步NoC架構需要具備精良且複雜的系統同步架構，此設計造成很大的成本和功率消耗。此論文我們提出一個非同步NoC (ANoC) 架構，利用非同步的連結設計以及可調適性路由器架構來解決此問題。路由器和連結設計主要是基於類延遲非敏感(Quasi Delay Insensitive) 邏輯電路設計。此設計讓提出之架構具備可延展性並且適合用於設計大型整體非同步地區同步系統架構 (Global Asynchronous Local Synchronous)。實驗結果顯示提出之ANoC 系統架構優於傳統的同步架構，尤其在規模較大的系統更可以彰顯其優越性。

 

Network-on-Chip (NoC) is a very practical and achievable approach to overcome bus limitation problems. However as NoC size increases, clock distribution becomes a major problem in Network-on-Chip systems. Large synchronous NoCs require a fine and complex design of clock tree which leads to large areas and high power consumption. In this paper, we propose an asynchronous NoC (ANoC) that features asynchronous links and asynchronous adaptive routing mechanism. Routers and links are based on Quasi Delay Insensitive (QDI) logic and they only require minimum timing assumptions. This makes the proposed design very scalable and suitable for large Global Asynchronous Local Synchronous Systems. The experiment results show that our proposed ANoC outperforms the synchronous NoC especially when the NoC size becomes large.