Parylene-Pocket Chip Integration

發表人：黃奎瑞(加州理工學院電機系博士班)

 

http://www.mems2009.org/

 

IEEE Weblink:

http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4805295&arnumber=4805491&count=291&index=190

 

近代在電子探針植入研究的成果造就了假肢神經系統技術的躍進，然而，由這些技術衍發出的設備大多遭受高信號噪音的影響，及昂貴的集成電路整合結構。本論文旨在探討一個利用矽晶片與簡單且具有伸縮性的PARYLENE(聚對二甲苯)膜囊的包裝技術，這個模囊可安置集成電路芯片及其他分立元件並為其提供電子傳導的連接作為示範，這工作使用這個技術引起8小腿硅探針列陣集成與一塊充分地功能16渠道放大器CMOS芯片。這些實驗結果可讓我們對於植入性設備的包裝整合及製作程序上做到最佳化。

 

Recent achievement in silicon probes implantation in the parietal cortex enables technological advances in neural prosthesis research. However, most of these technologies suffer from high signal-to-noise ratio and expensive integration scheme with IC chips or lack thereof. In this paper, we present a novel packaging technique that utilizes a simple, flexible parylene (chip) pocket on silicon substrate with

metal pads. This pocket can house an IC chip or a discrete component inside and provide electrical connections to it.  As a demonstration, this work uses this technique to produce an 8-shank silicon probe array integrated with a fully functional 16-channel amplifier CMOS chip.